Current hardware contains cross-die variation, which affects the ability of critical path timings to be met on a part by part basis. The known process of tuning parts for best case and worst case, or even for some type of statistical variation, does not provide enough margin, or is not adequately responsive to across-wafer or across-die variation.
Today's designs synthesize logic from a high level description based upon a set of files called timing assertions. These timing assertions define the arrival time of each input signal on every sub-unit of a design, and the required delay time of each signal leaving a timing unit. Due to variation of process, temperature and voltage, a set of Process/Voltage/Temperature corners, known as “PVT,” are selected to adequately verify the all units will meet the required timing assertions. Examples of PVTs would be Slow Process/1.0 V/125C which would be selected to verify that the unit meets the worst case conditions. Another example would be Fast Process/1.2V/−55C for a test of meeting the fast spec requirements.
While this technique was adequate in older technologies such as 180 nm or older, new technologies such as 90 nm or less are beginning to show increasing effects of cross die variation due to the small geometry effects and the tolerance of building such devices within these advanced technologies. As such, designs must utilize increasingly conservative approaches to provide adequate guard band to account for variations. because, even if a portion of a design may be closer to worst case performance, another portion of the path may have performance margin due to this process variation. In a similar manner, one area of the chip die may exhibit worst case process effects, while another section, due to cross-chip variation, has performance margin. With today's design techniques, designs are timed to meet the worst case conditions and cross-die variation assumptions, resulting in over-designed paths being integrated into the silicon.
The disadvantage of these fixed logic designs/paths is that even when regional margin or even total chip margin exists (for hardware not at slow process) paths within the design are optimized for worst case PVT and across-die matching. As result, designs burn excessive AC power during active state, and also leak the most leakage power during standby.